Does systemverilog has a way to generate a piece of code multiple times by just changing a piece of it with an integer?

SystemVerilog
1

Hi,

Is there a way in SV to do something like -

Code - run thrice and replace i with 1,2,3
begin
value_i = 22;
$display(“Value of x_i is %d”, value_i);
end

Result -
begin
value_1 = 22;
$display(“Value of x_1 is %d”, value_1);
end
begin
value_2 = 22;
$display(“Value of x_2 is %d”, value_2);
end
begin
value_3 = 22;
$display(“Value of x_3 is %d”, value_3);
end

Thank you in advance

2

In reply to prpatil:
There is no way to do this within SystemVerilog. You can use an external script or editor, or preferably use an unpacked array instead.

3

Okay. Thank you Dave.