Does Race Condition Exist in following Scenario :

SystemVerilog
,
1

Consider the following DUT code :


 module  DUT (  dut_intf   intf );
   logic [2:0] cntr ;

   always @( posedge intf.clk , negedge intf.rst_n )
    begin
       
       if( ! intf.rst_n )  cntr <= 0 ;

       else  cntr <= cntr + 1 ;

    end

   assign  intf.incr = cntr ;  //  Updated in Active Region  via  loopback  from  NBA  to  Active  Region .

 endmodule

Then within a Monitor Component :


   @( posedge vif_intf.clk );            //  Unblocks  in  Active  Region
 
      sampled_value  =  vif_intf.incr ;  //  Will  updated value be sampled ?

My question is whether a race condition exists while sampling ?
The value of incr is updated in re-entrant Active Region whereas in the Monitor Component there is no re-entrant active region

2

In reply to Have_A_Doubt:

There is no race condition with the code shown

The monitor picks up the old value of vif_intf.incr from the previous clock cycle. Assuming the clk’s are the same signal, both @(posedge clk) events happen in the same region before the update to cntr and intf.incr have happened.

However depending on what other code reads
sampled_value, you could have a race there.