Does Mentor "HDL designer" support systemverilog "interface" construct?

SystemVerilog
,
1

Hi,
we are about to perform design partition for verification activity. We would like to create wrappers around VHDL blocks
and connect them using systemverilog interfaces. In this way it is simpler to access signals, if needed, using an UVM
monitor.
We tried to create design top using HDL designer but it seems it does not “understand” system verilog interface construct
although it is specified on Mentor web site it shall be able to do it.
Is there any specific tool configuration that we shall do or did we miss any step while importing systemverilog code?

Thanks
/Dario

2

For any tool specific issues, it is highly recommended that you contact your vendor support team directly as they will be better able to help you.

HDL Designer does support SystemVerilog interfaces, but it is hard to provide more assistance without knowing more details about what you are doing.

3

In reply to cgales:

Hi,
thanks.
We are trying to import a design in block editor. The VHDL blocks are correctly imported but interfaces are not
imported. As far as I understood connections in block editor works only if they are compliant with verilog95.