Divide by zero

SystemVerilog
1

Dear,
Please let me know if the below code is supposed to throw run-time error.When I simulated the below code I won’t get any error rather the string is displayed and width value as unknown.
##################################

module test;

 reg [3:0]width;

 initial
   begin
     width = 4'd4/0;
     $display(width);
     #10;
   end


endmodule
2

In reply to sush:

Te “Arithmetic Operators” section of the Verilog standard defines division by zero as returning X. There’s nothing in the standard requiring a run-time error or message.

Regards

Mark

3

In reply to Mark Curry:

Thanks.