$display for `define -> not working

SystemVerilog
, ,
1

Hi All,

How can I display/print a `define value in Questa?

For the following code:

`define ABC ABC
initial $display("ABC = %s",`ABC);

I receive the following error message:

(vopt-7063) Failed to find 'ABC' in hierarchical name 'ABC'

So, what’s the problem?

Thank you!

2

In reply to ldm_as:


`define ABC "ABC"

module tb(); 
  
  string abc = `ABC;
  initial $display("ABC = %s",abc);
  
endmodule

This works and it has been tested on EDAplayground.
The quotes seem to play a big role and string variable too.

Cheers,
Stef

3

Thanks!