Disable Sequencer Sequence

UVM
1

Option1

//Configuration : disable subsequencers sequence

uvm_config_db #(uvm_sequence_base)::set(this, " .cpu_seqr_phase", “default_sequence”, null);

Option2:

virtual task start_item (
uvm_sequence_item item,
int set_priority = -1,
uvm_sequencer_base sequencer = null )

I want to disable the sequence/sequencer, can I use option2 like this?
start_item (tx, -1, null);

I was trying to find available options to disable the default sequencer/sequence, May I know which is recommended?

Kindly advice.

Question2:

Once the particular sequence/sequencer is disabled, how can it be enabled back?

Like, just calling

start_item(tx) or `uvm_do(tx)

Will this make the sequence/sequencer enabled back?

Thank You,
Mahesh

2

As you have discovered, using the “default_sequence” methodology has some significant drawbacks. For this reason, it is recommended to not use this methodology.

Instead, start any required “default” sequences as part of your test so you can maintain control over what is executing.