In reply to Jung Ik Moon:
The property should be written aa:
property p_test;
int t;
@(negedge clk) disable iff (!rstn || a)
$rose(b) |-> ##0 (1, t = 100)
##1 (b, t = t - 1)[*0:$]
##1 t <= 0; // <<<---
endproperty
A[*0] ##0 b // is a no match
A[*0] ##1 b // is same as "b"
//another option
property p_test;
int t;
@(negedge clk) disable iff (!rstn || a)
$rose(b) |-> ##0 (1, t = 100)
##1 (b, t = t - 1)[*1:$] // <<<---
##0 t <= 0;
endproperty
Aside from that, the disable should work as you described.
Try this change.
Ben Ben@systemverilog.us