Hi,
Can any body tell me what are the difference between normal test-bench and UVM test-bench.
Given the popularity of UVM (see link ) I think you could make a compelling argument that a UVM testbench is a ‘normal’ testbench
My guess is that in this context ‘normal’ testbench refers to something is using a simpler directed tests and not using an industry standard methodology such as UVM
In reply to alexgran:
Dear Can you please tell me what is the block level difference between normal system verilog test bench and uvm test bench.
In reply to piyush@cetpainfotech.com:
…compelling argument that a UVM testbench is a ‘normal’ testbench
UVM is gaining popularity, but I would not qualify it as “normal”.
UVM is a transaction-based, class-based, and constrained-randomization of stimulus style of testbench using a library of classes to facilitate some automation (with the cycling through the various phases) and reuse. However, for over 20 years, transaction-based style of architectures were used using Verilog and VHDL, obviously without classes or libraries. In fact, I described those styles in my VHDL and Verilog books. Some engineers, but most likely very few, still used directed tests. Thus, if I were to define a style for “normal”, I would rather say “transaction-based style”, which would then encompass UVM, VMM (still in use), and also the use of Verilog (prior to being SV) and VHDL.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115