Different handling of packed/unpacked arrays in assignment patterns?

SystemVerilog
,
1

Is the handling of assignment patterns differently for packed and unpacked arrays?

In the following example


  typedef logic logic_byte_u [7:0];
  typedef logic_byte_u logic_byte_array_u [3:0];
  logic_byte_array_u au;

  assign au  = '{logic: 1'b1, default: '0};

all bits of au would be 1.

What should happen in case of packed arrays instead?


  typedef logic [7:0] logic_byte;
  typedef logic_byte [3:0] logic_byte_array;
  logic_byte_array a;

  assign a  = '{logic: 1'b1, default: '0};

Is a == '1 or is a == '0?

Thanks and best regards,
Thomas

2

In reply to Thomas Kruse:

This is an open issue in the LRM.

I believe the intent was that type: and default: are both supposed to recursively descend until reach a simple packed array, i.e. a single dimensional packed array of bits. So the second example would only descend into the first dimension and logic would not be a match; A == '0.

3

In reply to dave_59:

Thanks a lot, Dave, for the fast reply!

Best regards,
Thomas