What are the differences in IP level and SOC level Verification?
What additional things we need to do in SOC level verification as compared to IP level?
Which kind of difficulties we face in SOC level Verification as compared to IP level verification?
Regards
cam
This is a very open-ended question since there are so many different levels of complexity involved with one person’s IP versus another person’s SOC. And since there are so many aspects of verification, I’ll just limit this discussion to the application of the UVM.
Generally the key issues with IP block verification are configurability and re-usability. If this IP block will be used in more than one place with configurable options, creating all the possible configurations could be quite a challenge since you can’t randomize the creation of RTL code. However, you can use a 2-step approach to use the randomization features of SV to generate a set of parameters to be used in a second simulation to configure your RTL code.
The other challenge of IP verification is making as much of the testbench reusable as possible at the SoC level. That means following the guidelines for configuring verification components as being active or passive. It also means making your code not sensitive to changes in hierarchy.
The key challenge of SoC Verification is usually how to manage the score boarding. Can you connect all the reference models used in IP verification to form a cohesive reference model, or do you have or need to create an independent reference model. There are various articles and papers on this subject.
Dave
please give some link articles and papers on this subject.
Regards
cammy