Difference of using always_comb or always inside testbench environment

SystemVerilog
1

System verilog has the statements like always_comb,always_ff.I believe these should be usefull in RTL coding.

Please clarify me will it make any difference of using always_comb or always in Testbench environment.

Thanks
Bharath

2

You can’ use these constructs inside of a class - only in a module or interface. They might have some use at the boundary between your DUT and testbench. However, these constructs were designed to specify the intent of how you want your synthesis tools to treat your RTL and eliminate mismatches between RTL and gate-level.