Hi I’m writing a code for arbiter that produces one hot signal as output when it sees the first bit of input as one. The c is a signal that propogates if it sees a one yet in the series. If i create a module of the below logic with the commented out line, it works but somehow when i turn it into a class it doesn’t. can anyone help me understand why?
class arbiter #(int n=8);
bit [n-1:0] r;
bit [n-1:0] g;
bit [n-1:0] c;
function new();
$display("%d",n);
c = 1;
endfunction
function void ccompute;
for(int i=1;i<n;i++) begin
c[i] = ~r[i-1] & c[i-1];
end
//c = {((~r[n-2:0]) & (c[n-2:0])),1'b1}; //why does this line not work in system verilog? whereas it works in verilog?
endfunction
function void gcompute(input bit[n-1:0] r=5);
this.r = r;
ccompute();
$displayb(c);
g = c & r;
endfunction
function void display();
$displayb(g,,
r,,c);
endfunction
endclass
module tb;
arbiter #(10) myarbiter;
initial begin
myarbiter = new;
myarbiter.gcompute(20);
myarbiter.display();
end
endmodule