Re usability is only the answer… if yes i think we can reuse the system verilog components.
why we go for UVM?
You are comparing 2 different things.
System Verilog is a language & UVM is methodology.
SystemVerilog builds on top of Verilog by adding abstract language constructs targetted at helping the verification process. One of the key additions to the language was the class. SystemVerilog classes allow Object Orientated Programming (OOP) techniques to be applied to testbenches. The UVM itself is a library of base classes which facilitate the creation of structured testbenches. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation.