Difference between full case Vs parallel case and casex Vs casez

SystemVerilog
1

Can anyone help me to understand exact differences between full case and parallel case and also difference between casex and casez, if possible with coding examples?

2

In reply to Naresh_Kumar:

[“full_case” & “parallel_case” Evil Twins!

](http://www.sunburst-design.com/papers/CummingsSNUG2005Israel_SystemVerilog_UniquePriority.pdf)Difference between casex and casez