Difference between const and const static construct

SystemVerilog
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1

Hi ,
Can somebody explain the difference between the two statements below

const static string type_name = "some_text";
const string type_name = "some_text";
2

In reply to srikanthen:

The difference depends on the context of where these declarations appear and affect when these variables get allocated and initialized, and their visibility outside the context. For example, if these were inside a class, the static form gets initialized before time 0 and is accessible using the class scope operator. The non-static form gets initialized when the class gets constructed and is only accessible via a class reference.

But if you just want to associate a symbolic name with a literal, it is best to use

parameter string type_name = "some_text";

This give you the widest possible use of ‘type_name’