break statement can end a loop. disable can be used to disable a named block.
If i use a disable statement to end a loop (named block) then how is it different from break statement.
In reply to Madhan S:
Use break, not disable to exit a loop.
The disable statement ends a named block and not necessarily the block you are currently in. If you have multiple concurrent activations of a named block, the disable statement ends all of them. This is from legacy Verilog.
The break statement is only for getting out of the loop you are currently executing, and there’s no need to put the loop in a named block.