In reply to dave_59:
One more thing to add on Dave’s reply:
I read the ##0 as the start of a new sequence that starts in the same time
step as the end point of the preceding sequence. Thus,
@( posedge clk ) a |=> $rose(b) ##0 $rose( c );
It’s a different connotation than the logical && that represents combinational logic.
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.
or Cohen_Links_to_papers_books - Google Docs
Getting started with verification with SystemVerilog