Determining whether type parameter is Signed or Unsigned?

SystemVerilog
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6

In reply to ABD_91:

A parameter with an explicit data type in its declaration always keeps it type. The RHS default or any override cannot change the parameter’s type. That value will be implicitly cast to the declared type.

Main2::SIZE will always be unsigned. Main2::m::SIZE becomes unsigned because Main2::SIZE is unsigned.

This is my interpretation of the LRM.