In reply to dave_59:
LRM 6.20.2 ::
"A parameter declaration with no type or range specification shall default to the type and range of the final value assigned to the parameter, after any value overrides have been applied. If the expression is real, the parameter is real.
If the expression is integral, the parameter is a logic vector of the
same size with range [size-1:0] ."
Since override in our case is 2 ** 32 - 1 , the expression is integral .
So the parameter is a logic vector ( 4-state ) of size [31:0] .
Since 2 ** 32 - 1 is signed decimal by default , Main1::SIZE is logic signed [31:0]
Also could you please elaborate on ::
" any override must be assignment compatible with declared type"
class Main2 has an explicit datatype ( unsigned ) , so irrespective of the
overridden value ( 2**32 - 1 via m2 in our case )
Both Main2::SIZE and Main2:
:SIZE would ALWAYS be unsigned right ?