Deposit/Force functionality for real datatypes with hierarchy provided as a string

UVM
,
1

Hi,
I would like to have a way of forcing signals by providing a hierarchical string to a variable similar to uvm_hdl_deposit() or uvm_hdl_force(), with the targeted variable being of real datatype.

The prototypes of uvm_hdl_* methods use uvm_hdl_data_t type, which appears to be defined as a logic vector.


typedef logic [UVM_HDL_MAX_WIDTH-1:0] uvm_hdl_data_t;
import "DPI-C" context function int uvm_hdl_deposit(string path, uvm_hdl_data_t value);

I am aware that I could use SystemVerilog’s built-in “force /release” operators which work fine with real data types, however, as stated above, I would like to provide the hierarchy as a string. (String because the hierarchies shall be provided dynamically from some lookup table)

Do you know a way how to achieve this by means of any existing features or do you think it will be neccessary/possible to have custom VPI implementation for that?

Thank you for your responses.

2

In reply to pmoos:

You can copy the code from uvm_hdl_deposit and create a new function that works with reals.