Delay after and before assignment in SV

SystemVerilog
,
1

Hi,

What is the difference between below 2 codes?

initial begin
a=0; b=1;
a = #3 1;
c = #5 a + b;
end

initial begin
a=0; b=1;
#3 a = 1;
#5 c = a + b;
end

What is the difference between delay after the ‘=’ and before the variable name?

Thanks.

2

two type of delay is there 1.regular delay 2. intra delay
regular delay we define like below

initial begin
a=0; b=1;
#3 a = 1;
#5 c = a + b;
end

the meaning of this is at simulation time “0” a=0 and b=1
at simulation time “3” a=1
at simulation time “8” c=a+b
this above all you defined that regular delar.

intra delay we define like below

initial begin
a=0; b=1;
#5;     //              modified your code here by me   see this is the blocking right so in the blocking regular delay add with the intra delay so at simulation tim"5" a=0; b=1;                      
a = #3 1;  //   here at simulation time "8" at that time the value of the a=1;
#5;              //    modified your code here by me 
c = #5 a + b; //  5+3+5+5=18 so at simulation time"18" c=a+b; 
end

this below code add by me

initial begin
a<=0; b<=1;//see this is the non blocking code so in this the intra delay is not add with the regular delay
#5;           at "5" a=0 and b=1
a <= #3 1;
#5;          at "10" a=1; 
c <= #5 a + b;
end
3

In reply to jaswanth_b:

Any procedural statement can have a number of optional delay controls in front of it, as long as the procedural block is in a place that allows delays (i.e. you cannot have delays inside a procedural function)

initial begin
    a = 0;
    #1 a = 1;
    #2 #3 a =3;
    #4 $display($time);
end

is the same as

initial begin
    a = 0;
    #1;
    a = 1;
    #2;
    #3;
    a =3;
    #4;
    $display($time);
end

Using the ; here makes no difference, both display time as 10. But there are places where it matters whether there is one statement or multiple statements.

initial begin
    if (condition1) 
       #4 $display($time);
    if (condition2) 
       #4; $display($time); // the $display is not part of the if statement. 
end

The intra-assignment delay statement is left over from very early Verilog before non-blocking assignments were added to the language. They no longer should be used. Basically

A = #delay B;

is equivalent to

begin 
   temp = B;
   #delay
   A = temp;
end

You ahould instead use
A <= Delay B;
which delays the assignment to A without blocking the flow of procedural statements.

4

Thank you both for answering.