Define unrecognized by modelsim simulator

SystemVerilog
1

I’ve defined the following define in the top level module.

top.sv
`define UE_LINK_ENTRY top.testcase.test_mgr(“LINK_ENTRY”)

a leaf module uses the following code:
leaf.sv
ifdef UE_LINK_ENTRY if (UE_ENABLE_VAR) begin UE_LINK_ENTRY;
$display(“TEST”);
end
`endif

with the simulators like vcs and ncsim, I’m able to see the display statement TEST in the log file. But modelsim is not able to recognize the above definition. Giving (vlog-2163) Macro `UE_LINK_ENTRY is undefined compilation error for leaf.sv file.

I’ve redefined it as follows, then able to simulate the test successfully.

    `ifdef UE_LINK_ENTRY
    `define UE_LINK_ENTRY top.testcase.test_mgr("LINK_ENTRY")
    if (UE_ENABLE_VAR) 
      begin
         `UE_LINK_ENTRY;
         $display("TEST"); 
      end 
    `endif

Please suggest how to handle this problem in the top file? Why the define is not visible in the leaf module?
This is not a concern with vcs and ncsim only with modelsim.

Thanks & Regards,
Cooldude

2

I think that by default Questa compiles each file separately.

I think it works if you add the compile switch -mfcu.

3

In reply to shalom:

Thanks a lot. Its working :)