Default value of static and non-static data members

SystemVerilog
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1

What is the default value of static and non-static data members in systemverilog? Is it 0? I’m familiar with C++ programming. In C++, by default, static data members are initialized to 0 and non-static ones are initialized to a garbage value.
I ran a small piece of code on EDA Playground, sharing it here:

class static_display;
  static int s;
  int n;
endclass
program playground;
  initial begin
    static_display obj=new;
    $display("n:%0d",obj.n);
    obj.n++;
    $display("n updated:%0d",obj.n);
    $display("s:%0d",static_display::s);  
    static_display::s++;
    $display("s updated:%0d",static_display::s);
  end
endprogram

Output:
n:0
n updated:1
s:0
s updated:1

2

In reply to akshaymote:

All variables initialize to a default value according to their data type. It does not matter if they are static or non-static.

3

In reply to dave_59:

What is the default value in case of static data members? Is it 0?

4

In reply to akshaymote:

As I said the initial value only depends on the variable’s data type. For int it is 0. See table 6-7 for other types in the 1800-2012 LRM.

5

In reply to dave_59:
Thanks for the reference. Just summing things up:
In c++, an int variable takes up garbage value if not initialized. If it is declared as static int instead, the default value then becomes 0 instead of any garbage value.
int c;//initializes to garbage value
static int cpp;//initializes to 0
In systemverilog, a two state int has default value as 0, four state integer has default value as x. Declaring the variable static or not doesn’t make any difference to default value in systemverilog.
int c;//default is 0
static int sc;//default is 0
integer n;//default is x
static integer sn;//default is x
The default value comes from the default values defined for a particular data type in LRM.
Link to LRM: http://ieeexplore.ieee.org/document/6469140/
check table 6-7