Declaring an array to store real values

SystemVerilog
,
1

Hi All,
I want to create one array to store the real value also I want to randomize it. My intention is to create an array which can store real values and then picking out unique value out of range say 10 to 12 and value could be 10.2, 10.5, 11.5, 11.7 and so on… but that should be a real value. So far I was able to implement everything but I don’t know how should I declare my array as real and rand.


class packet;
  rand bit [5:0] a[] ;  // Here I want to use the type as real something like as rand real bit [5:0] a[]; 
  constraint c1 { a.size()==10;
               }
  constraint c2 { foreach (a[i])
    a[i] inside {[10:12]};
                }  
  constraint c3 { unique {a};
               }
  function void display();
    $display("Values are:%p", a);
  endfunction
endclass

  module tb;
    packet pkt;
    initial begin
      pkt = new();
      pkt.randomize();
      pkt.display();
    end
  endmodule

Thanks and Regards

2

you can try to use “real” type to replace “bit [5:0]”.

3

In reply to skyhome0911:

A variable can be either real or integral. There is no built-in fixed point types in SystemVerilog.

Randomization of real types is something that was just added to the upcoming IEEE 1800-2023 standard. Most tools have already implemented some of it, check with your vendor.

If you want to do this the way the LRM is currently written, you can scale the number in post_randomize.

class packet;
  rand int ai[] ; 
  real ar[];
  constraint c1 { ai.size()==10;
               }
  constraint c2 { foreach (ai[i])
    ai[i] inside {[10_00:12_00]};
                }  
  constraint c3 { unique {ai};
               }
  function void post_randomize();
     ar = new[ai.size()];
     foreach (ar[i]) ar[i] = ai[i]/100.0;
  endfunction
  function void display();
    $display("Values are:%p", ar);
  endfunction
endclass