Declare interface signal as per condition

SystemVerilog
,
1

Hello All

I have a doubt where I want to change the value driven to the ports in an interface based on a condition. What would be the best way to do that :

Code example

Abc_if if1(
.a(try1),
.b(try2)
);

Now I want to give try3 to a and try4 to b if condition say ( if control is 1 ) and give a the value try1 and b the value try2 if control is 0. Can I do that. So based on condition I want to drive two different values to the port inputs. Suppose if else doesn’t work inside.

2

In reply to Verrockon.:

I’m not following what you want to do. Can you try posting some code that did not work and explained what it did versus what you expected it to do.

3

In reply to dave_59:

In reply to Verrockon.:
I’m not following what you want to do. Can you try posting some code that did not work and explained what it did versus what you expected it to do.

Sure I have an interface to which I want to drive input based on a condition. Let that condition be x in the testbench. Now if x is 10 I want to drive try1 and try2 to the ports of the interface instantiated in the testbench and if x is 20 I want to drive try3 and try4 to respective interface ports. Suppose the if else won’t work in this case which I tried.

timescale 1ns/1ns;
‘define x X_VAL // coming from outside the tb
‘Define Param_1 (1,2,6)
module Tb;

Abc_if ‘Param_1 inst (
.a(try1),
.b(try2)
);

endmodule

So now based on value of x I want to drive try3 and try4 to ports a and b of above interface if x is 20, else keep driving the values try1 and try2 to interface as it is.

4

In reply to Verrockon.:

Hello check this out: (hope it helps)

Simply put and AND/OR/NOR… gate on the connection which will reflect your conditions or how the conditions should be gating or not the signals driven.


interface myif (
    input logic try1,
  	input logic try2,
  	input logic try3,
  	input logic try4
);

    //Interface Signals

endinterface

// Not Synth module in case of Synth module a clocked procedural block needs to be used
module Driver;
  // declare
  bit val, clk;
  // Driven signals
  logic Dtry1,Dtry2;
  logic Dtry3,Dtry4;
  // these are the condition to be met
  bit c1, c2;
  
  // clk gen
  always #10 clk = ~clk;
  
  // main interface
  myif i_f(
    .try1	(Dtry1 & c1),
    .try2	(Dtry2 & c1),
    .try3	(Dtry3 & c2),
    .try4	(Dtry4 & c2)
  );
  
  // put signals drive to 1 for simplicity
  initial begin
    Dtry1 = 1;
    Dtry2 = 1;
   	Dtry3 = 1;
    Dtry4 = 1;
  end
  
  // run
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars();
    #100;
    val = 1;
    #100;
    val = 0;
    #100;
    $finish();
  end
  
  // Run driver
  always @(val) begin
    drive();
  end
  
  // DRIVER
  task drive();
    if(val) begin
      c1 = 1; c2 = 0;
    end
    else begin
      c1 = 0; c2 = 1;
    end
  endtask
endmodule