Dealing with bidirectional signals via classes

SystemVerilog
1

hello everyone!
Straight to the case: i have bidirectional signal “data” and i have to operate with it in the object of the class. I used clocking block to write data in this signal, like this:

wait (first_if.cb1.data);
second_if.cb2.data <= first_if.cb1.data ^ breaking_code;

as you see, i have to transmit data from one interface to another with some modifications. but data in “second_if” appears one clock period later, than it appears in “first_if”. Is it because i use wait (first_if.cb1.data)? I’ve read, that such a style is not recommended, when using clocking blocks… And if so, how do i put data without time delay?
And one more question: is there any way to communicate with bidirectional signals without clocking blocks? They make design more complex, as to me.
Thank you for reading this!=)

2

In reply to trogers:

Clocking block is used to drive signals synchronusly with respect to a clock. So when you try to update a signal using clocking block the output will get reflected only after the current event. You cannot have the signal captured at the same clock.

If the design can be driven asynchronusly then you can drive the signal without clocking (just to have immediate effect). This works well if both the clocks are not same and they are having fixed phase difference.

3

You should only use clocking block events when dealing with clocking block signals. Assuming cb1 and cb2 are exactly the same clock, you can do

@(first_if.cb1 iff first_if.cb1.data)

Otherwise you look at my DVCon paper in the section on bi-directional signals.

4

In reply to dave_59:

thank you, Dave, as usual=) Still, i didn’d understand from that topic, if i can communicate with these signal without cb, if i have multiple drivers?

5

In reply to trogers:

Yes, you can have multiple drivers using the same techniques a designer would use in RTL. Use an enable to turn a continuous assignment on or off, or simply assign the variable on the RHS of the assignment to 'z when you don’t want it to drive.

interface itf;
  logic signalvar = 'z, enable = 0; // procedurally assign from testbench
  wire signal;
  assign signal = enable ? signalvar : 'z;

  // or 
  assign signal = signalvar; // set to 'z to turn off
endinterface
6

In reply to grey:

I don’t really understand the context of your question. Have you looked at my paper referenced above.

7

In reply to grey:

My DVCon paper explains this exact problem and gives a solution.