In reply to ben@SystemVerilog.us:
Bout is the output of the counter CNTR, it goes to comparator to check whether it’s 0 or not 0. If it becomes 0, we stop the process, otherwise again the addition happens.
In reply to ben@SystemVerilog.us:
Bout is the output of the counter CNTR, it goes to comparator to check whether it’s 0 or not 0. If it becomes 0, we stop the process, otherwise again the addition happens.