D Flip Flop UVM Test bench

UVM
1

I am running a D flip flop test bench and getting Timeout error. I tried with putting display debug statements but it is hanging immediately post compilation.
Execution interrupted or reached maximum runtime.
Exit code expected: 0, received: 137

Link to the testbench - EDA Playground

2

In testbench.sv

  • You’re missing calling run_test()
  • Setting the virtual interface needs to be updated something like uvm_config_db#(virtual dff_if)::set(null,"*","vif",vif);

In test.svh

  • No main_phase nor run_phase
3

Thanks, this helped.