Cyclic randomization behavior without 'randc' keyword

SystemVerilog
, , ,
3

In reply to bachan21:

class abc;
  rand logic[2:0] a;
  int saved[$];
  
  constraint c1 { !(a inside saved);}
  
  function void post_randomize();
    saved.push_back(a);
    if(saved.size == 2**3)begin
      saved = {};
    end 
  endfunction
  
endclass

module abc;
  abc a1;
  
  initial begin
    a1 = new();
    repeat(8)begin
    a1.randomize();
    $display(a1.a);
    end
  end 
endmodule