Cross of a cross

SystemVerilog
,
1

Hi,

I was going through the System Verilog LRM IEEE 1800-2015 and did not find a feature where we can do cross of a cross bins.
Can somebody confirm if this feature will be allowed or already introduced by the IEEE in its new release.

I have embeded an example below which shows cross of a cross and it works fine with Questa 10.4b
with a note “Creating cover cross ‘csr_2’ from other crosses (i.e. ‘csr_1’) is an extension to SystemVerilog”.

module crs_crs;
 
  bit a,b,c;

  covergroup cg;
    option.per_instance = 1;
    
    ca:coverpoint a
    {
      bins zero = {0};
      bins one = {1};
    }

    cb:coverpoint b
    {
      bins zero = {0};
      bins one = {1};
    }

    cc:coverpoint c
    {
      bins zero = {0};
      bins one = {1};
    }

    csr_1: cross ca, cb
    {
      bins oo = binsof(ca.zero) && binsof(cb.zero);
    }

    csr_2:cross csr_1, cc
    {
      bins bc_00 = binsof(csr_1.oo) && binsof(cc.zero);
      bins bc_11 = binsof(csr_1.oo) && binsof(cc.one);
    }

  endgroup
   cg inst;

  initial
  begin
    inst= new();
    b=0;c= 0; inst.sample();
    b=1;c= 1; inst.sample();
  end

endmodule
2

In reply to kamlesh kumar:

The current LRM does not allow to specify a cross of another cross. In the area of covergroups, the LRM falls far behind what is actually implemented by most vendors in terms of errata and enhancements.