Eda playground link is dff_vip_nocfg - EDA Playground Could you please help in resolving this error. TimeScale is 1 ns / 10 ps Error-[XMRE] Cross-module reference resolution error driver.sv, 55 Error found while trying to resolve cross-module reference. token ‘vif’. Originating package ‘test_…

In reply to sharan587 : Try this version： [image] EDA Playground Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

In reply to jianfeng.he : Hi Your code in the mentioned eda link is working. What was the mistake from my code. Could you please elaborate and I did not see any uvm_info print after compiling your code because run_test is not called is my conclusion correct? Thanks P Sharan

In reply to sharan587 : You are completely right. And there are more weaknesses in the code provided which are tolerated by VCS. You should clean-up your code and insert diagnostic messages to see the progress when starting the simulation. The key problem is you do not constructt your analysis port…

In reply to chr_sue : Hi I have modified the code and added uvm_info statements but when I run this code no other uvm_info is printed except uvm_error which is defined in scoreboard. Could you please tell me what am I missing? [image] EDA Playground Edit, save, simulate, synthesize Syste…

In reply to sharan587 : There is more not working. Please give me another day to fix rhe issues.

In reply to chr_sue : Sure. Look at it in your free time no issues. Thanks Sharan

In reply to sharan587 : Can you please respond to my email christoph@christoph-suehnel.de I have downloaded your example to work locally. I can send you my solution which still needs some adoption wrt to the monitor handling.

In reply to chr_sue : Sure I will respond and send you an email regarding this. Thanks Sharan

Cross module reference error

UVM

jianfeng.he February 26, 2023, 11:19am 2

In reply to sharan587:
Try this version：