Cross coverage with ignore bin

SystemVerilog
, ,
6

In reply to dave_59:

I can figure out only first part, for which information is complete.

cross cA, cB, cC, cD {
  // Your requirement is (a_bin[0] or a_bin[1]) x cB x cC x cD.
  // i.e either a_bin[0] x cB x cC x cD 
  //         or a_bin[1] x cB x cC x cD should be considered. 
  //         
  // So, it seems me there must a condition (Decoding) for it. 
  // This conditions should be passed while creating this cg.
  ignore_bins my_ignore = { (<condition>) ?  binsof(cA) intersect {0} : binsof(cA) intersect {1} }; 
}