Cross coverage with ignore bin

SystemVerilog
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2

You can use the intersect operator:


cross cA, cB, cC, cD {
  ignore_bins my_ignore = binsof(cA) intersect {1, 2} &&
    binsof(cB) intersect { cB.b1 } && binsof(cC) intersect { cC.c1 };
}

I’m not sure if instead of intersect { 1, 2 } you could say intersect { cA.a_bin }, so you’re just going to have to try it out. Would be nice of you to post the conclusion, too.

More info in section 19.6.1 Defining cross coverage bins of the SV-2012 LRM.