Cross coverage of cross items

SystemVerilog
1

Has anybody tried the cross of crosses within the covergroup.
for example
class cg_c;
rand bit [1:0] x, y;
rand bit z;

covergroup cg;
xy : cross x, y;
xyz : cross xy, z; // LRM doesn’t specify anything like this. Is this a valid code.
endgroup
endclass

For simplicity I have given a small example. Is it valid to write cross coverage with cross items?

Thanks,
Shiva.

2

This isn’t standard syntax. QuestaSim allows this, but specifically mentions that this is an extension to SystemVerilog so that you know that this code might cause problems when switching vendors.

I’ve tried it out with another Big Three vendor and there it’s also supported with a special compile switch.

3

In reply to Tudor Timi:

Thanks Tudor Timi.

I did tried that code with Questa simulator, it specifies that particular code as System Verilog extension.
Just wanted to confirm, whether it is legally supported. Now I got my answer.

Thanks,
Shiva.