Creating random constraints for overlapping sequence detector

SystemVerilog
, ,
1

I am trying to write constraint for overlapping sequence detector, let’s say pattern is 101101. How can I cover all overlapping cases. This case is bit simpler, there may more complex pattern that I may not be able write constraints for all overlapping patterns. How to write a constraint in such a way that I should be able cover correct patterns, invalid patterns, overlapping patterns etc., overlapping patterns are 10101101,10110101101

My understanding:

class seq_item;
  rand bit data;
  bit [5:0] pattern = 6'b101101;
  constraint pat{ data  dist{0:=33, 1:=67};}
  constraint c2{foreach(pattern[i]){
    soft data == pattern[i];
     }
}

endclass

I understanding, I am not covering all cases including overlapping. How to write constriant covering all cases?

2

I think it would be easier to just generate a series of unconstrained random bits and use a cover directive to make sure your detector detected the pattern, as well as detecting the pattern at least twice less than the width of the pattern.

Here’s a test that checks to see if your pattern can overlap.

module top;
  class seq_item;
    bit [7:0] pattern = 8'b0000001;
    parameter int psize = $bits(pattern);

    bit iterator[] = new[psize]; // just to iterate over psize in sum()
    rand bit [psize*2-2:0] test_overlap;
    constraint c_overlap {
      iterator.sum() with (int'(test_overlap[item.index+:psize] == pattern)) == 2;
    }
  endclass
  
  seq_item h = new;
  
  initial begin
    if (h.randomize())
      $display("%b has overlap",h.test_overlap);
        else
          $display("no overlap");
  end
endmodule