Why are components not created in build phase and not in run phase?
I am aware, build phase is for creating components so that before start of simulation we have a definite hierarchy which we do not intent to change?
What can go wrong if we create a component in run_phase or for a matter of fact in any other phase?
In reply to vdb_sie:
https://verificationacademy.com/forums/uvm/top-down-bottom-build-connect-phase
this link is useful to understand its need.
Components can only be created in the build phase. Why? If you created component X during the run phase, UVM would have to call its build, connect, … phases, but this would make X out of phase (literally) with every other component.
The real question is why do you want to create components during the run phase. That implies your testbench topology changes halfway through the test. Which means your design grew new capabilities.
Build all the components at the start. You can always have them stay silent until needed.