Creating associate array

SystemVerilog
1

lets take an normal array IP : S = {1, 2, 3, 4, 5, 6, 7, 8, 7, 6, 3, 1, 100, 555}
Create a associative array, in which the elements of above array are index and number of occurrence is the content
Expected output : A[1] = 2 A[2] = 1 A[100] = 1…etc

2

In reply to shashikanth123:

module top;
  int S[] = {1, 2, 3, 4, 5, 6, 7, 8, 7, 6, 3, 1, 100, 555};
  int A[int] = '{default:0};
  initial begin
    foreach(S[i]) A[S[i]]++;
    $display("A = %p",A);
  end
endmodule
3

In reply to dave_59:

Hi Dave,
it seem that it still work even if not initialize associate array
is it a good habit to initialize associate array before using?
Thanks

4

In reply to peter:

Yes, you are supposed to get a warning if you try to read an associative array element before it has been allocated (section 7.8.6 Accessing invalid indices).

But many tools cater to lazy SystemVerilog coders who don’t want to deal with warnings.