Creating a register value object

SystemVerilog
1

Hi,
I’m trying to create an object of a register value and assign it to the register array.

I have a register array of 16 registers , each of 32 bits. bit [31:0] reg_array [16];

I need to create a register value object and assign it to the register array every time I do a try_next_item and fetch a uvm_sequence item that has reg_access set to 1 and the sequence_item will have the register number I have to associate the register value to.

Like:

reg_array[0]
reg_array[1]
reg_array[2]
reg_array[3]
…

When I do a try_next_item , if the sequence_item received has reg_access set , a reg_value object has to be created and assigned to the appropriate reg_array[n] . The value of n is from the sequence_item.

How can I “create a register value object (The register value is an int or a bit[31:0]) and assign to say, reg_array[3]”? Can you please provide some pointers to achieve this?

Thanks

2

In reply to Ramyas:

Can you please tell why you want an object to represent register value?

Where is reg_array[16] located, in the driver?

If both reg_access flag and reg address “n” are from sequence_item, have you considered to have register value “bit [31:0] reg_value” to be a data of sequence_item as well?