Create a SVA $PAST based on two different clock events

SystemVerilog
,
1

I’m looking for a SVA that is based on two different clock events and then a compare with $PAST.

Stripped pseudo RTL:

FF_slow <= FF_fast @slow_clk
FF_fast <= rand_data @fast_clk

pseudo SVA:

@(posedge slow_clk) |->
@(posedge fast_clk) |->
FF_fast == $PAST(FF_fast,2,1,@posedge fast_clk);

I haven’t seen this example before. Is this possible to do?
/PP

2

In reply to PP:

Looks legal. The only thing is the startup. The fix:
##2 @(posedge slow_clk) |->
@(posedge fast_clk) |->
FF_fast == $PAST(FF_fast,2,1,@posedge fast_clk);

Can also do the following, which is more readable because the first implication opr is not needed

##2 @(posedge slow_clk) ##0 @(posedge fast_clk) |->
FF_fast == $PAST(FF_fast,2,1,@posedge fast_clk);
Ben systemverilog.us