Covert array into vector

SystemVerilog
,
3

In reply to d_g:

Hi, I did it using shifting . Please go through it and let me know whether it’s ok or not with respect to your requirement.


module x;
  bit [7:0] payload[64];
  bit [511:0] data;
  
  initial begin
    payload[0] = 2;
    payload[1] = 1;
    
    foreach(payload[i])
      begin
        if(i<=1)continue;
        payload[i] = ((payload[i-1]+payload[i-2])%21==0 ? 1 : (payload[i-1]+payload[i-2])%21); // For getting small numbers (in the range 1 to 20)
      end
    
    foreach(payload[i])
      begin
        $display("%0d",payload[i]);
      end
    $display("\n");
    
    for(int i=0;i<63;i++) begin
      data = data<<8;
      data [7:0]=payload[i];
      $display("%0d",data[7:0]); // for checking whether it's working or not
    end
   
    
     $display("%0b",data);
    
  end
  
endmodule