Covergroups inside VHDL code

In reply to chr_sue:

Thank you Chris!! That was so well explained!
But I still have a couple of doubts.

In numbers (2) and (3) could we say class instead of modules? I say that because the only module I have is the Top module, the rest are interfaces and classes.

Could I bind my coverage class to the DUT? I guess what I should do is to bind my interface to the DUT and then use that interface to pass some data to the coverage class right?

Thank you