Covergroups inside VHDL code

UVM
7

In reply to antonio92m:

Ok, I’m starting to explain:

  1. WhereToBind: we can bind to a (1) certain design. This the entity name of a VHDL design or the module name of a Verilog/SV design. If you have more than 1 instances of this design in your DUT. The bind-block appears in all instamces. (2) we can bind to an instance.Then WhereToBind is the instance name of the design we want to bind to (using the dot-notation,i.e. DUT.inst1.inst2)

  2. WhatIsBindedToTheData: this is the module name where you have your coverage model inside (covergroups, cross etc.

  3. NameOfTheBindInstance: This is the instance name of your module holding the coverage model.

  4. SignalIWantToBindInTheVDHLArchitecture: you can connect your bind-module to any signal inside a VHDL instance or design. But you cannot connet to any VHDL variable.

Hope this helps you to better understand what is going on with the bind construct.