In reply to chr_sue:
Thanks for your answer chr_sue!
Also thanks for my wording.
It is not clear yet for me how to bind a SV block to a VHDL architecture.
The example says:
module bind_wrapper;
bind send_receive receive_send inst_receive_send (.data_received(data_sent));
endmodule
I guess I can bind my interface to the VHDL architecure, Am I right? But I do not really know how to.
By observing the “bind_wrapper” module and the files it seems the syntax would be:
bind WhereToBind WhatIsBindedToTheData NameOfTheBindInstance (.VariableThatHoldTheDataBinded(SignalIWantToBindInTheVDHLArchitecture));
And then I would need to pass this data to my coverage class, would I send the SV variable binded to the architecture to the monitor that my coverage class is subscribed?
Thank you thank you!!
Antonio