Covergroups inside VHDL code

UVM
3

In reply to dave_59:

Sorry for the late reply…
Thank you for your answer, you really guided me!
I found your article which is really good “The Missing Link: The Testbench to DUT
Connection”

About the bind construct, you really pointed me in a great direction but I am still a bit lost. I guess I have to use it in my test module/class with syntax similar to:

bind DUT: InterfaceName InterfaceInstanceNAme
    .InterfaceVariable(DUTSignal_1)
    .InterfaceVariable(DUTSignal_i)
    ....
);

Is there any website/book where I could find how to use most of the SV Syntax aspect?
I am using the Ray Salemi UVM Primer book but there are some aspects like the bind trick I cannot find in it.

Dave the thing you mention about the tool limitations. I am using questasim so I do not have any problems. However I would like to have a code which also could be simulated in a different simulator. If possible…

Thanks,
Antonio