Antonio,
You want to look at the bind construct of SystemVerilog. This allow you to insert a module instance inside another module instance (or entity in VHDL) without modifying the original module. The bind construct was originally intended to insert assertions into a DUT without modifying the source, but you could certainly do the same for covergroups or any other construct.
When it comes to VHDL<->SystemVerilog inter-operability, there may be specific limitations that may be tool specific. Check you User Manual or vendor for assistance.
Dave