In reply to antonio92m:
Hi Antonio,
regarding
(1): It would be still a UVM environment. Because the bind construct is used heavily for SystemVerilog assertions. And it adds in the toplevel module only one additional unit.
(2): common:: indicates that data aree following are defined in the package ‘common_pkg’. It is the resolution operator.
Regarding the code example, please use my email address from my webpage. The I’ll respond to you.
I believe it is not so easy to understand, because it is an apptroach using so-called abstract classes. But I’ll help you and guide through the code.
Finally it is up to you to mention me if you feel I could help you.