Covergroups inside VHDL code

UVM
18

In reply to chr_sue:

Hello Chris,

Thanks again, I really appreciate it.

About:

  1. I am not sure about this option because then it would not have an UVM structure and it would be “unreausable and unmanageable code” right?

  2. I have read the article several times and it is not clear yet for me. The code in the appendix A where the bind is.
    I do not understand the meaning of the colon “:”. Would it be the same using VHDL?


bind model : dut.sub1 probe_itf #(.WIDTH(common_pkg::WordSize1)) m1_1(InternalBus);
bind model : dut.sub2 probe_itf #(.WIDTH(common_pkg::WordSize2)) m1_2(InternalBus);
bind model : dut.sub1 probe_itf #(.WIDTH(1)) m1_3(CS);

Also regarding that I do not have submodules, would the structure of the bind construct change? I mean if I do not have a module and submodules compared with the Dave Rich article I think it should be like:


bind scrambler : DUT bind_bfm bind_bfm_inst(.scrambler_reg(registro_act));
/*where the bind_bfm is the interface*/

I have also visited your website. Do you know the link where you will publish it?

I also wanted to ask you. I am trying to learn the UVM because of my final project for uni. Do you mind if I write your name as one of the people that helped me a lot?