Covergroups inside VHDL code

In reply to antonio92m:

Hello Antonio,

I took my time to investigate soem more details and I found the story with the additional interface is not so easy as I just said. You have now 2 options:
(1) You can implement your design covergroups in the interface/module you are binding to your design. But this is not so nice because you have to take care regarding the sampling of your covergroup.
(2) You spend more effort as explained in a paper presented at DVCon by Dave Rich (Mentor Graphics). If you google ‘missing link dvcon’ you should find it. I can provide you also a code example. I’m working on it and you can get it tomorrow evening. Please contact me through my web-page christoph-suehnel@web.de