Covergroups inside VHDL code

In reply to chr_sue:

Hello Chris,
I have been trying to use the bind construct but I did not succeed.
I have created a new interface that will be registered with the factory and therefore the coverage class will access to it. Then I declared the bind construct in the following way:

bind designEntity NewInterfaceName NewInterfaceInstance (.VariableOfTheNewInterface(DesignSignalIwannaBeBindedTo);


module top;
   import uvm_pkg::*;
   import scrambler_pkg::*;
`include "scrambler_macros.svh"
`include "uvm_macros.svh"


   scrambler_bfm       bfm();
   scrambler DUT (.clk(bfm.clk), .reset(bfm.reset), .d_in(bfm.d_in),
		  .v_in(bfm.v_in), .d_out(bfm.d_out), .v_out(bfm.v_out));

   /*New interface binded to the internal data*/
   bind_bfm bind_bfm_inst();

   bind scrambler bind_bfm bind_bfm_inst(.scrambler_reg(registro_act));

   
initial begin
   uvm_config_db #(virtual scrambler_bfm)::set(null, "*", "bfm", bfm); //Registering the main interface with the factory
   uvm_config_db #(virtual bind_bfm)::set(null,"*","bind_bfm",bind_bfm_inst);//Registering the bind interface with the factory
   run_test();
end

endmodule : top

The new interface is very simple


interface bind_bfm;
   import scrambler_pkg::*;

   bit [6:0] scrambler_reg;
endinterface : bind_bfm



And the signal I want to get is a:


signal registro_act: std_logic_vector( 6 downto 0);

But Questa complains:

** Error: top.sv(13): (vopt-1027) Number of positional association elements (1) exceeds number of formals (0).

I do not know what that error means. Could you please give me a hand?

Thank you!