this are the types of bins in SystemVerilog coverage:-
-Implicit bins(automatic bins)
-Explicitly bins
-Transition bins
-Wildcard bins
-Ignore bins
-Illegal bins
is there any other types of bins is there for functional coverage?
this are the types of bins in SystemVerilog coverage:-
-Implicit bins(automatic bins)
-Explicitly bins
-Transition bins
-Wildcard bins
-Ignore bins
-Illegal bins
is there any other types of bins is there for functional coverage?